Expert of Memory Solution Team (New Architecture, High-speed interface)

• Architected DDR/LPDDR/stacked-memory systems for AI-oriented like-stacked architectures.
• Led path-finding for like-stacked memory solutions targeting future AI accelerators.
• Guided analog design for Like-LPDDR5 PHY and protocol-level implementation.
• Designed Tx/Rx, EQ, ZQ-Cal, DCC/DCM, LBT, and LDO high-speed IP blocks.
• Recognized as a core contributor and key expert in Memory Architecture (2024.06.22).
• AI 지향 적층형 메모리를 위한 DDR/LPDDR/Stacked-Memory 아키텍처를 설계했습니다.
• Like-LPDDR5 PHY, Tx/Rx, EQ, ZQ-Cal, DCC/DCM, LDO 등의 고속 IP를 지도·설계했습니다.

Director of Design Group (High-Speed IO and Datapath Department)

• Directed IO/Datapath teams for LPDDR4x/DDR4 PHY and architecture development.
• Designed Tx/Rx, EQ, LDO, Op-Amp, and SerDes (S2P/P2S) for LPDDR4x interfaces.
• Guided DLUT-based row-hammer mitigation and BL Sense-Amp offset-cancellation schemes.
• LPDDR4x/DDR4 PHY와 아키텍처 개발을 위한 IO/Datapath 조직을 이끌었습니다.

Senior Manager → Senior Principal Circuit Engineer & PM

• Achieved China’s first 1x-node DDR4 working die for the 8Gb Test Vehicle and led DDR4/DDR5 architecture evolution through 2023.
• Led 16Gb DDR4 (1b) Process Vehicle and 16Gb DDR5 (1c+) Test Vehicle development with tape-out, working-die, timing/power closure, and cross-functional execution.
• Developed DLUT row-hammer mitigation, wREF, data-alignment, anti-fuse, SerDes, DFT logic, IO circuits, and BL Sense-Amp offset-cancellation.
• Defined cell-core architecture, datapath/IO guidelines, and layout strategy across multiple DRAM technology nodes.
• 2018년부터 2023년까지 CXMT에서 중국 최초 1x DDR4 Working Die, 16Gb DDR4 PV, 16Gb DDR5 TV를 포함한 DRAM 아키텍처와 회로 개발을 통합적으로 이끌었습니다.

Principal Circuit Design Engineer

• Designed high-speed BIST logic, double-LFSR data-recovery schemes, and core 3D-NAND datapath architecture.
• Built interface-chip architecture reducing capacitive loading with TDC re-timing and SerDes.
• Implemented low-swing data-line, high-speed datapath, and double-SerDes schemes for 3D-NAND.
• Received multiple Core U.S. Patent Awards for BIST, interface-chip, low-swing signaling, and IO sense amplifier innovations.
• 3D-NAND 고속 BIST, 인터페이스 칩, 저전압 스윙, Double-SerDes를 설계했습니다.

Principal Engineer of Memory System-level Verification and Quality

• Led semiconductor memory SCM strategy, technical negotiation, and technology-roadmap alignment.
• Served as LG’s JEDEC representative for LPDDR4, WIO2, eMMC5.x, and UFS-related platform discussions.
• Directed TFT initiatives for smartphone memory competitiveness and semiconductor cost reduction.
• Selected for LG Next Leader / Talented Leader Pool (2013, 2014).
• LG의 JEDEC 대표로 활동하며 LPDDR4, WIO2, eMMC5.x 관련 플랫폼 논의에 참여했습니다.

Senior Circuit Design Engineer

• Designed digital/analog/mixed-signal circuits for LPDDR2/LPDDR3 products.
• Developed LPDDR2/LPDDR3 datapath architecture, test-mode circuits, and low-power full-chip schemes.
• Invented write-alignment architecture for ring-back failure and led on-chip monitoring tool development.
• LPDDR2/3 Datapath, 테스트 모드, 저전력 전체 칩 구조와 Write-Alignment 구조를 개발했습니다.

Staff Process Architecture & Integration Engineer → Senior Circuit Design Engineer

• Developed DRAM cell/capacitor front-end process sequence and device windows for 256M DRAM.
• Led circuit and full-chip development across LPDDR1, DDR1, Rambus DRAM, and One-DRAM products.
• Pioneered the world’s first LPDDR1 and built One-DRAM IP / patent portfolio.
• Received Samsung CEO Best Circuit Design Engineer Award (2004).
• 256M DRAM 공정 통합에서 출발해 LPDDR1, DDR1, Rambus DRAM, One-DRAM 전체 칩 개발을 이끌었습니다.
• 세계 최초 LPDDR1 개발과 One-DRAM 특허 포트폴리오를 구축했습니다.