HBM Architecture · Analog / Mixed-Signal · High-Speed TxRx
HBM 아키텍처 · Analog/Mixed-Signal · 고속 인터페이스
권경환 / 權敬桓
I design AI-era memory architectures where power, bandwidth, timing, latency, and manufacturability must close together — working at the boundary of HBM architecture, analog/mixed-signal design, and system-level memory path-finding.
전력·대역폭·타이밍·레이턴시·제조성이 동시에 수렴해야 하는 AI 시대의 메모리 아키텍처를 설계합니다 — HBM 아키텍처, Analog/Mixed-Signal, 시스템 레벨 메모리 Path-finding의 경계에서.
+3 Filed 미국 특허
+3 출원
// HBM Cube Architecture — Conceptual
System Profile
엔지니어 프로파일
Engineer. Architect.
Innovator.
엔지니어. 아키텍트.
혁신가.
I'm Kyounghan (Kelvin) Kwon — a semiconductor memory engineer with 27+ years designing the circuits that power the world's most demanding AI and mobile computing systems.
My career spans Samsung → SK Hynix → LG Electronics → CXMT → JSC → Huawei HKRC → Micron Technology, crossing Korea, China, Hong Kong, and Texas. Each chapter opened a new technical frontier — from LPDDR to 3D-NAND to HBM path-finding for the AI era.
27년 이상 AI·모바일 컴퓨팅 시스템을 구동하는 회로를 설계해온 메모리 반도체 엔지니어 권경환(Kelvin)입니다.
What distinguishes my work is a consistent method: identify the real bottleneck, connect architecture with circuit reality, and drive solutions that can survive timing, power, area, process, and product constraints.
I do not treat architecture, circuits, and manufacturability as separate layers. I treat them as one engineering conversation that must close together.
제가 일하는 방식의 핵심은 같습니다. 진짜 병목을 찾고, 아키텍처를 회로 현실과 연결하며, 타이밍·전력·면적·공정·제품 제약 속에서도 버틸 수 있는 해법으로 밀어붙이는 것입니다.
저는 아키텍처, 회로, 제조 가능성을 분리된 층으로 보지 않습니다. 결국 함께 수렴되어야 하는 하나의 엔지니어링 대화로 봅니다.
"At Full Blast, you're giving it your all."
Education
Korea University
고려대학교
M.S. Electrical Engineering · 1998 · GPA 4.1/4.5 · Samsung Scholarship
전기공학 석사 · 1998 · GPA 4.1/4.5 · 삼성장학금
Career Log
경력 로그
27+ Yrs · 7 Companies · 4 Geographies
28년 · 7개 회사 · 4개 지역
From transistor-level process integration and the world's first LPDDR1 to next-generation HBM Cube architecture — each chapter widened the bridge between device physics, circuit design, and system architecture.
트랜지스터 레벨 공정 통합과 세계 최초 LPDDR1부터 차세대 HBM Cube 아키텍처까지 — 각 경력은 소자 물리, 회로 설계, 시스템 아키텍처를 잇는 폭을 넓혀왔습니다.
MTS (Member of Technical Staff) of HBM Architecture
HBM core-die structure · timing/area trade-offs · cross-functional closure
- Defined next-generation HBM core-die architecture (Cell/Datapath) and floorplan strategies for PPA.
- Architected core-die structure and chip-size optimization for high-speed HBM operation.
- Analyzed DRAM core behavior and optimized AC/DC parameters aligned with JEDEC specifications.
- Integrated device–process–packaging–system viewpoints for advanced HBM stack design.
- 차세대 HBM 코어다이 아키텍처(Cell/Datapath)와 PPA 중심 플로어플랜 전략을 정의했습니다.
- 고속 HBM 동작을 위한 코어다이 구조와 칩 크기 최적화를 주도했습니다.
Expert of Memory Solution Team (New Architecture, High-speed interface)
HBMx path-finding · LPDDR5-like protocol · mentoring and architecture guidance
- Architected DDR/LPDDR/stacked-memory systems for AI-oriented like-stacked architectures.
- Led path-finding for like-stacked memory solutions targeting future AI accelerators.
- Guided analog design for Like-LPDDR5 PHY and protocol-level implementation.
- Designed Tx/Rx, EQ, ZQ-Cal, DCC/DCM, LBT, and LDO high-speed IP blocks.
- Recognized as a core contributor and key expert in Memory Architecture (2024.06.22).
- AI 지향 적층형 메모리를 위한 DDR/LPDDR/Stacked-Memory 아키텍처를 설계했습니다.
- Like-LPDDR5 PHY, Tx/Rx, EQ, ZQ-Cal, DCC/DCM, LDO 등의 고속 IP를 지도·설계했습니다.
Director of Design Group (High-Speed IO and Datapath Department)
LPDDR4x / DDR4 PHY · IO and datapath leadership · DLUT guidance
- Directed IO/Datapath teams for LPDDR4x/DDR4 PHY and architecture development.
- Designed Tx/Rx, EQ, LDO, Op-Amp, and SerDes (S2P/P2S) for LPDDR4x interfaces.
- Guided DLUT-based row-hammer mitigation and BL Sense-Amp offset-cancellation schemes.
- LPDDR4x/DDR4 PHY와 아키텍처 개발을 위한 IO/Datapath 조직을 이끌었습니다.
Senior Manager → Senior Principal Circuit Engineer & PM
China first 1x DDR4 working die · DDR4/DDR5 vehicle leadership · DLUT / wREF
- Achieved China’s first 1x-node DDR4 working die for the 8Gb Test Vehicle and led DDR4/DDR5 architecture evolution through 2023.
- Led 16Gb DDR4 (1b) Process Vehicle and 16Gb DDR5 (1c+) Test Vehicle development with tape-out, working-die, timing/power closure, and cross-functional execution.
- Developed DLUT row-hammer mitigation, wREF, data-alignment, anti-fuse, SerDes, DFT logic, IO circuits, and BL Sense-Amp offset-cancellation.
- Defined cell-core architecture, datapath/IO guidelines, and layout strategy across multiple DRAM technology nodes.
- 2018년부터 2023년까지 CXMT에서 중국 최초 1x DDR4 Working Die, 16Gb DDR4 PV, 16Gb DDR5 TV를 포함한 DRAM 아키텍처와 회로 개발을 통합적으로 이끌었습니다.
Principal Circuit Design Engineer
3D-NAND datapath · interface-chip innovation · low-swing signaling
- Designed high-speed BIST logic, double-LFSR data-recovery schemes, and core 3D-NAND datapath architecture.
- Built interface-chip architecture reducing capacitive loading with TDC re-timing and SerDes.
- Implemented low-swing data-line, high-speed datapath, and double-SerDes schemes for 3D-NAND.
- Received multiple Core U.S. Patent Awards for BIST, interface-chip, low-swing signaling, and IO sense amplifier innovations.
- 3D-NAND 고속 BIST, 인터페이스 칩, 저전압 스윙, Double-SerDes를 설계했습니다.
Principal Engineer of Memory System-level Verification and Quality
JEDEC representation · sourcing strategy · smartphone memory competitiveness
- Led semiconductor memory SCM strategy, technical negotiation, and technology-roadmap alignment.
- Served as LG’s JEDEC representative for LPDDR4, WIO2, eMMC5.x, and UFS-related platform discussions.
- Directed TFT initiatives for smartphone memory competitiveness and semiconductor cost reduction.
- Selected for LG Next Leader / Talented Leader Pool (2013, 2014).
- LG의 JEDEC 대표로 활동하며 LPDDR4, WIO2, eMMC5.x 관련 플랫폼 논의에 참여했습니다.
Senior Circuit Design Engineer
LPDDR2 / LPDDR3 datapath · low-power architecture · write-alignment innovation
- Designed digital/analog/mixed-signal circuits for LPDDR2/LPDDR3 products.
- Developed LPDDR2/LPDDR3 datapath architecture, test-mode circuits, and low-power full-chip schemes.
- Invented write-alignment architecture for ring-back failure and led on-chip monitoring tool development.
- LPDDR2/3 Datapath, 테스트 모드, 저전력 전체 칩 구조와 Write-Alignment 구조를 개발했습니다.
Staff Process Architecture & Integration Engineer → Senior Circuit Design Engineer
World-first LPDDR1 · One-DRAM IP · DRAM process-to-architecture foundation
- Developed DRAM cell/capacitor front-end process sequence and device windows for 256M DRAM.
- Led circuit and full-chip development across LPDDR1, DDR1, Rambus DRAM, and One-DRAM products.
- Pioneered the world’s first LPDDR1 and built One-DRAM IP / patent portfolio.
- Received Samsung CEO Best Circuit Design Engineer Award (2004).
- 256M DRAM 공정 통합에서 출발해 LPDDR1, DDR1, Rambus DRAM, One-DRAM 전체 칩 개발을 이끌었습니다.
- 세계 최초 LPDDR1 개발과 One-DRAM 특허 포트폴리오를 구축했습니다.
// Career Geography
High-Impact Innovations
핵심 기술 성취
8 Defining Breakthroughs
8대 기술 브레이크스루
Intellectual Property
지식재산권
9 Granted U.S. Patents (+3 Filed)
등록 9건 + 출원 3건 미국 특허
// Patent Topology
Representative highlights: US12374378B2 extends the DLUT family for Row-Hammer monitoring and refresh control, while earlier patents in low-swing signaling, interface-chip architecture, BIST, and input/data-path design show a repeated pattern of turning circuit insight into product-level advantage.
대표 특허 하이라이트: US12374378B2는 DLUT 계열의 Row-Hammer 모니터링/리프레시 제어를 확장한 최신 결과입니다. 그 이전의 저전압 스윙, 인터페이스 칩, BIST, 입력/데이터패스 특허들은 회로 통찰을 제품 경쟁력으로 연결해온 흐름을 보여줍니다.
| Patent No.특허 번호 | Domain기술 | Date등록 | |
|---|---|---|---|
| US12374378B2 | Row Hammer DLUT | 2025-07-29 | CXMT |
| US10504606B2 | BIST / DRAM Test | 2019-12-10 | SKH |
| US10068624B2 | Interface Chip | 2018-09-04 | SKH |
| US9543904B1 | Diff Amp Sensing | 2017-01-10 | SKH |
| US9621165B2 | Low-Swing Tx/Rx | 2017-04-11 | SKH |
| US9070429B2 | Write Alignment | 2015-06-30 | SKH |
| US8477543B2 | Data Input Strobe | 2013-07-02 | SKH |
| US8120986B2 | Multi-port Memory | 2012-02-21 | SAM |
| US6980036B2 | Freq Multiplier | 2005-12-27 | SAM |
| US20160373066A1 | Diff Amp Circuit | Filed 2015 | SAM |
| US20130127498A1 | Power-up Signal | Filed 2013 | SAM |
| US20040093478A1 | IC Signal One Pin | Filed 2003 | SAM |
⚠ A1 patents: listed under SAM per user-requested homepage labeling
Thought Leadership
기술 인사이트
Insights on Memory & AI
메모리 & AI 기술 인사이트
The Memory Wall Was Never a Bandwidth Problem
메모리 월은 처음부터 대역폭 문제가 아니었다
After 27 years designing memory interfaces, I've seen this pattern repeat: the industry chases bandwidth while latency quietly becomes the real bottleneck for AI inference workloads.
27년간 메모리 인터페이스를 설계하며 반복되는 패턴을 목격했습니다. 업계는 대역폭을 좇지만, AI 추론에서 진짜 병목은 레이턴시입니다.
DLUT: A New Architecture for Row-Hammer Defense
DLUT: Row-Hammer 방어의 새로운 아키텍처
US12374378B2 — my latest patent uses a Dynamic Look-Up Table to achieve +95% Row-Hammer defense rate. The architecture intuition behind it.
US12374378B2 — DLUT를 활용한 +95% Row-Hammer 방어율 달성. 그 아키텍처 직관을 공유합니다.
Why PIM vs. CXL Is the Wrong Question for HBM5
HBM5에서 PIM vs. CXL은 잘못된 질문이다
The real question isn't where to put the compute — it's how to eliminate round-trip latency entirely. After 2 years path-finding HBMx, here's my framework.
진짜 질문은 컴퓨팅을 어디에 두느냐가 아니라, 왕복 레이턴시를 어떻게 제거하느냐입니다.
Near-Memory Compute
Memory Pooling
1.2TB/s
2TB/s+
Latency-first Architecture
Establish Connection
연결 시작
Let's talk
memory.
메모리에 대해
이야기합시다.
I welcome conversations on HBM and advanced memory architecture, AI-era memory direction, high-speed interface design, technical speaking, mentoring, and advisory opportunities where deep engineering judgment matters.
HBM과 차세대 메모리 아키텍처, AI 시대 메모리 방향성, 고속 인터페이스 설계, 기술 강연, 멘토링, 자문 등 깊이 있는 엔지니어링 판단이 필요한 대화를 환영합니다.
Open For
협업 가능 분야
- 🔬 Architecture Discussion — HBM / DRAM / AI Memory Systems
- 🎤 Technical Speaking — HBM, AI Memory, Analog IC
- 📐 Analog / Mixed-Signal and High-Speed IO Consultation
- 📋 JEDEC Standards Advisory
- 🧭 Next-Generation Memory Path-finding
- 🎓 Mentoring — Early-Career Memory Engineers
- 🔬 아키텍처 리뷰 — HBM / DRAM 시스템 설계
- 🎤 기술 강연 — HBM, AI 메모리, Analog IC
- 📐 Analog / Mixed-Signal 회로 컨설팅
- 📋 JEDEC 표준 자문
- 🧭 차세대 메모리 Path-finding
- 🎓 후배 메모리 엔지니어 멘토링